1. Field of the Invention
The present disclosure generally relates to fully depleted (FD) devices in advanced semiconductor techniques and, more particularly, to semiconductors devices having fully depleted channels and a method of forming such a semiconductor device.
2. Description of the Related Art
In modern electronic technologies, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the ongoing demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than one micrometer, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than any discreet circuit composed of independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors), and passive elements, such as resistors and capacitors, integrated on a semiconductor substrate with a given surface area, wherein typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a FET is that of an electronic switching element, wherein a current through a channel region formed between two junction regions, referred to as source and drain, is controlled by a gate electrode, which is disposed over the channel region and to which a voltage relative to source and drain is applied. In common FETs, the channel region extends along a plane between the source and drain regions, such FETs also being referred to as “planar FETs.” Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON state” and a non-conducting state or “OFF state” may be achieved. It is important to note that the characteristic voltage level at which the conductivity state changes (usually called “the threshold voltage”) therefore characterizes the switching behavior of the FET. In fact, it is an ongoing issue in present semiconductor fabrication to keep variations in the threshold value level low for implementing a well-defined switching characteristic. However, as the threshold voltage depends nontrivially on the transistor's properties, e.g., materials, dimensions, etc., the implementation of a desired threshold voltage value during fabrication processes involves careful adjustment and fine-tuning during the fabrication process, which makes the fabrication of advanced semiconductor devices increasingly complex.
The continued miniaturization of semiconductor devices in the deep sub-micron regime becomes more and more challenging with smaller dimensions. One of the several manufacturing strategies employed herein is the implementation of SOI technologies. SOI (silicon-on-insulator) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and short channel effects, thereby, improving performance. Semiconductor devices on the basis of SOI differ from conventional semiconductor devices formed on a bulk substrate in that the silicon junction is formed above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon-on-sapphire or SOS devices). The choice of insulator depends largely on the intended application, with sapphire being usually employed in high performance radio frequency applications and radiation-sensitive applications, and silicon dioxide providing for diminished short channel effects in microelectronic devices.
In general, a conventional SOI-based semiconductor device comprises a semiconductor layer, e.g., based on silicon and/or germanium, being formed on an insulating layer, e.g., silicon dioxide, which is a so-called buried oxide (BOX) layer formed on a semiconductor substrate. From a physical point of view, the very thin semiconductor film over the BOX layer enables the semiconductor material under the transistor gate, i.e., in the channel region of the semiconductor device, to be fully depleted of charges. The net effect is that the gate can now very tightly control the full volume of the transistor body. Accordingly, an SOI device is much better behaved than a bulk device, especially because the supply voltage, i.e., the gate voltage, gets lower and device dimensions are allowed to be scaled.
Basically, there are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) devices. For example, in an N-type PDSOI device, a P-type film is sandwiched between a gate oxide (GOX) layer and the buried oxide (BOX) layer which is to be large, such that the depletion region does not cover the whole channel region. Therefore, PDSOI devices behave to some extent like bulk semiconductor devices.
A major problem, particularly in PDSOI, is the so-called “floating body effect” (FBE), which appears because the semiconductor film over the BOX layer is not connected to any of the supplies.
In FDSOI devices, the semiconductor film between the GOX layer and the BOX layer is very thin, such that the depletion region substantially covers the whole semiconductor film. Herein, the GOX layer supports less depletion charges than in bulk applications, and, accordingly, an increase in inversion charges is caused, resulting in higher switching speeds. Additionally, FDSOI devices do in general not require any doping of the channel region. In FDSOI, drawbacks of bulk semiconductor devices, like threshold voltage roll off, higher sub-threshold slop body effect, short channel effect, etc., are reduced. The reason is that source and drain electric fields cannot interfere due to the BOX layer bordering the very thin semiconductor film along a depth direction of the SOI substrate.
Current semiconductor devices on the basis of SOI include a silicon layer of 5-10 nm thickness formed on a BOX layer with a thickness of about 145 nm.
Further scaling of SOI devices for fabricating semiconductor devices of the next generation raises new problems and challenges. For example, when reaching the next technology node, the thickness of the channel region has to be further reduced, turning out to be critical in current semiconductor technologies. However, the relaxing of the semiconductor channel raises new constraints on a thickness of the semiconductor film and of the BOX layer because of issues relating to the electrostatic control of strongly scaled SOI devices.
Accordingly, it is desirable to provide a semiconductor device which partially overcomes at least one of the above-mentioned issues.